代码收藏家 STM32L4xx LCD时钟源LSI应用
stm32l4xx时钟配置
问题
在stm32l433应用中，采用芯片自带lcd驱动断码屏，原板卡采用LSE作为时钟源。
新板卡采用LSI作为时钟源。本文档记录配置过程，及踩坑经历。
配置过程
采用stmcube生成程序配置。关于LSI配置如下：
LL_RCC_LSI_Enable();
/* Wait till LSI is ready */
while(LL_RCC_LSI_IsReady() != 1)
{
}
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);
LL_RCC_EnableRTC();
运行发现运行到这，
HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
{
uint32_t tickstart = 0x00;
/* Get timeout */
tickstart = HAL_GetTick();
/* Loop until FCRSF flag is set */
while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
{
if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
{
hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
返回HAL_TIMEOUT。
推测为LSI没有正常给lcd。
###调试
通过Registers 查看寄存值，RCC -> RTCSEL 应该为0x02,现在为0x00,手动赋值，发现赋值不成功。
查看手册
The bits of the Backup domain control register (RCC_BDCR) are outside of the VCORE
domain. As a result, after Reset, these bits are write-protected and the DBP bit in the
Section 5.4.1: Power control register 1 (PWR_CR1) has to be set before these can be
modified. Refer to Section 5.1.4: Battery backup domain on page 130 for further
information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a
Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or external
Reset will not have any effect on these bits.
需要寄存器PWR_CR1的DBP位置位
Bit 8 DBP: Disable backup domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
LL库程序如下：
LL_PWR_EnableBkUpAccess();
LL_RCC_LSI_Enable();
/* Wait till LSI is ready */
while(LL_RCC_LSI_IsReady() != 1)
{
}
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);
LL_RCC_EnableRTC();
作者：红叶知秋
